DFT Engineer

Job Description

Requirements
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### Must have:

### - We require 5+ years of practical experience in DFT and ATPG for SoC or ASIC designs. - We expect a strong command of DFT fundamentals, including controllability, observability, and scan-based test methods. - We need proven experience with ATPG pattern creation, analysis, and troubleshooting. - We require hands-on exposure to MBIST, including memory test architectures and diagnostic techniques. - We value knowledge of IO test approaches for interface and pin-level validation. - We expect a solid understanding of clock DFT and clock verification principles. - We require a strong foundation in digital design and RTL fundamentals. - We expect experience using industry-standard DFT and ATPG EDA tools. - We need someone who can perform well in fast-paced, high-performance semiconductor programs. - We require strong analytical thinking, problem-solving ability, and communication skills. - We require a BE or equivalent educational background.

Responsibilities:
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- We will rely on you to develop and support DFT and ATPG solutions for SoC and ASIC designs. - We will expect you to apply scan-based testing concepts to improve controllability and observability. - We will have you generate, analyze, and debug ATPG patterns. - We will count on you to implement and validate MBIST solutions and memory diagnostics. - We will have you support IO test planning and validation at the interface and pin level. - We will expect you to contribute to clock DFT planning and clock verification activities. - We will need you to work closely with digital design and RTL teams to ensure testability goals are met. - We will expect you to use standard DFT and ATPG EDA tools effectively in daily engineering tasks. - We will rely on you to contribute in a high-energy semiconductor environment and collaborate across programs. - We will expect you to communicate findings clearly and help resolve technical issues efficiently.
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Company:
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We are hiring a DFT Engineer for our onsite team in San Jose, CA. Our work focuses on high-performance semiconductor programs, and we offer the opportunity to contribute to complex SoC and ASIC test solutions in a fast-paced engineering environment. We value strong collaboration, technical depth, and clear communication, and we are looking for someone who can bring hands-on expertise to our design-for-test efforts.
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