Vensure Employer Solutions
US - Florida - Melbourne
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The engineer will be responsible for RTL design and simulation, developing UVM test environments, and supporting DO-254 certification. They will also manage the full hardware lifecycle from requirements to design and synthesis.
Requirements: Candidates should have strong FPGA/ASIC verification experience of at least 5 years and familiarity with DO-254 documentation and processes. The ability to mentor and coordinate remote teams, along with strong communication skills, is also required.
Key Skills: FPGA Verification, DO-254 Compliance, SystemVerilog, UVM, VHDL, Verilog, Static Timing, Linting, CDC Analysis, Xilinx FPGA, RTL Design, Simulation, Test Environments, Certification, Hardware Lifecycle, Communication Skills
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