Remote | ASIC/SoC Hardware Design & Verification Engineer — $65–$95/hour

Job Description

**We are sharing a specialised part-time consulting opportunity for US-based ASIC and SoC engineers with hands-on experience in RTL design, functional verification, hardware debugging, IP integration, timing closure, or production silicon development.**

This role supports an advanced AI initiative focused on improving how models understand and solve real-world semiconductor engineering problems. Selected engineers will create realistic chip design and verification tasks, develop complete reference solutions using SystemVerilog or Verilog, evaluate model-generated responses, and apply practical engineering judgment gained through design, debugging, verification, and tapeout workflows.

**Key Responsibilities**

**Hardware Engineering Task Development**

* Design realistic ASIC and SoC engineering problems based on practical industry experience
* Create tasks involving RTL implementation, debugging, functional verification, microarchitecture, integration, or optimisation
* Develop scenarios that reflect genuine engineering challenges rather than textbook exercises
* Define clear technical requirements, constraints, expected behaviour, and evaluation criteria

**RTL Design \& Reference Solutions**

* Write accurate reference RTL using SystemVerilog or Verilog
* Develop supporting testbenches, assertions, specifications, and technical documentation
* Create solutions covering combinational and sequential logic, control paths, datapaths, interfaces, and subsystem behaviour
* Ensure reference implementations are technically sound, reproducible, and appropriately challenging

**Verification \& Model Evaluation**

* Run engineering tasks against AI models and assess the correctness of generated solutions
* Identify issues in logic, implementation, protocol handling, verification methodology, and technical reasoning
* Evaluate whether proposed designs satisfy functional, architectural, and performance requirements
* Explain model strengths, weaknesses, and failure modes through clear written technical feedback

**Technical Quality \& Collaboration**

* Review tasks and solutions developed by other hardware specialists
* Maintain consistent standards for technical rigor, realism, complexity, and completeness
* Collaborate with engineers across design, verification, formal methods, synthesis, and integration disciplines
* Contribute to shared evaluation frameworks and quality-calibration activities

**Ideal Profile**

**Strong candidates may have:**

* Hands-on experience in ASIC or SoC design, functional verification, formal verification, or related semiconductor engineering
* Strong fluency in SystemVerilog, Verilog, or both
* Experience with production silicon, tapeout, IP development, chip integration, or subsystem verification
* Solid knowledge of interface protocols, handshaking, backpressure, multiple clock domains, and multi-module dataflow
* Experience working independently on complex design or verification problems
* Strong written communication and the ability to explain hardware engineering decisions clearly
* Reliable availability for approximately 20--40 hours per week

**Educational Background**

* A degree in electrical engineering, computer engineering, electronics engineering, computer science, or a related technical field is highly relevant
* Graduate students, recent graduates, and experienced industry professionals may all be considered
* Advanced academic or professional work in digital design, semiconductor systems, computer architecture, or verification is valuable
* Equivalent hands-on engineering experience may also be considered

**Nice to Have**

* Experience with RTL design, microarchitecture, or custom IP development
* Background in IP integration, bring-up, or system configuration involving NoC, PCIe, DDR, ARM, or AXI
* Experience with UVM, SVA, CocoTB, testbench architecture, or coverage-driven verification
* Familiarity with formal verification, property checking, and coverage closure
* Knowledge of synthesis, timing analysis, power-performance-area optimisation, or physical design considerations
* Experience in analog or mixed-signal design verification
* Familiarity with tools such as Synopsys VCS, Cadence Xcelium, Siemens Questa, VC Formal, or Verdi
* Experience with open-source tools such as Icarus Verilog, Verilator, Yosys, CocoTB, or OpenROAD
* Previous involvement in AI evaluation, training-data development, technical annotation, or model benchmarking

**Why This Opportunity**

* Apply practical semiconductor engineering expertise to advanced AI development
* Create realistic tasks grounded in actual chip design and verification work
* Evaluate how AI systems approach complex RTL, debugging, and hardware-reasoning problems
* Collaborate with engineers across multiple ASIC and SoC specialisations
* Work remotely with a flexible part-time commitment and competitive hourly compensation

**Contract Details**

* Part-time W-2 contingent employment arrangement
* Fully remote role available to candidates based in the United States
* Expected commitment of approximately 20--40 hours per week depending on availability
* Candidates should have confirmed availability without scheduling conflicts
* Competitive rates between $65--$95 per hour depending on expertise and project scope
* Work may include onboarding, technical calibration, task development, model evaluation, and peer review
* Project scope, workload, and duration may be adjusted according to programme requirements and performance

**About the Platform**

This opportunity is available through 24-MAG LLC. We connect experienced professionals with remote consulting opportunities across technical, evaluation, and project-based workstreams.

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