NVIDIA AI
US - California - Austin
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Invent new optimization engines to increase chip frequency and minimize power consumption by fusing independent design steps. Develop and improve C++ algorithms for gate-level sizing, buffering, and incremental parasitic extraction.
Requirements: Requires a Master's or PhD in Electrical Engineering or Computer Science with experience in VLSI algorithm development using C++. Candidates should understand VLSI timing optimization and be familiar with design implementation tools like ICC2 or Innovus.
Key Skills: VLSI Physical Design Algorithms, C++, Sizing, Buffering, Clock Tree Synthesis, Legalization, Place and Route, Timing Optimization, Perl, Tcl, Python, Multithreading, Distributed Computing, Reinforcement Learning, Graph Neural Networks, Machine Learning
Benefits: Equity, Benefits
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