Design Engineer III

Job Description

#### Job Description

Onsite 3 days in Sunnyvale, CA  

Job Description  
About the role: Design Verification engineer for wearables silicon accelerator IPs --- testbench development, coverage-driven verification, RTL debug, and power/performance measurement.  
Responsibilities  
Develop and execute verification plans for RTL blocks/IPs across the subsystem.  
Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests.  
Drive functional coverage and assertion (SVA) closure; run and triage regressions.  
Perform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feed back to design/power-modeling teams.  
Build power/perf dashboard for tracking and publishing  
Debug RTL failures (waveform/Verdi) and provide actionable feedback to the design team/verification team.  
Contribute to automation of verification/regression and power/performance measurement flows (Python).  

Minimum Qualifications  
Proven SystemVerilog + UVM verification experience (testbench architecture, sequences, drivers/monitors).  
Functional coverage, constrained-random, and assertion-based verification (SVA); coverage closure.  
Strong RTL debug with industry simulators (VCS / Xcelium / Questa) and waveform tools (Verdi).  
Working knowledge of RTL design principles and digital design fundamentals.  
Proficiency in Python (or Perl) scripting for automation.  

Preferred Qualifications  
Experience with power measurement tools --- PrimeTime PX (PTPX) or equivalent (e.g., PrimePower).  
Low-power / power-aware verification (UPF, power-aware sim) in advanced nodes (7nm and below).  
Formal verification and/or emulation (Palladium / Zebu) experience.  
Familiarity with the RTL-to-GDSII flow.  
Data analysis / ML approaches for coverage or debug triage.  
Previous Meta experience preferred.  

Education: BS in Electrical/Computer Engineering or Computer Science required; MS preferred (not required).