Lead Software Engineer - Low Power Verification

Job Description

Lead the improvement of UPF debug features and performance for Palladium and Protium emulation platforms. Develop AI-assisted debug tools and rebuild end-to-end documentation for multi-billion-gate low-power designs.

Requirements: Requires a degree in CS, EE, or a related field with experience ranging from 1 to 4+ years depending on the degree level. Proficiency in IEEE 1801 UPF, RTL languages, C++, and AI-assisted coding tools is essential.

Key Skills: IEEE 1801 UPF, SystemVerilog, Verilog, VHDL, C++, Object-Oriented Design, Root-Cause Analysis, Technical Writing, AI-Assisted Coding, Low Power Verification, Debugging, Software Engineering

Benefits: Paid Vacation, Paid Holidays, 401(k) Plan With Employer Match, Employee Stock Purchase Plan, Medical Insurance, Dental Insurance, Vision Insurance