Lead Software Engineer - Low-Power Verification

Job Description

The role involves improving UPF compilation performance and correctness for Palladium and Protium platforms while adding support for new IEEE 1801 LRM revisions. The engineer will also rebuild end-to-end workflow documentation and deploy UPF solutions across key flows like AVIP and UVMA.

Requirements: Candidates need a degree in CS, EE, or a related field with experience ranging from 1 to 4+ years depending on the degree level. Proficiency in RTL languages, C++, scripting (Perl, Tcl, Python), and technical writing is required.

Key Skills: IEEE 1801 UPF, SystemVerilog, Verilog, VHDL, C++, Object-Oriented Design, Perl, Tcl/Tk, Python, AI-assisted coding, Technical writing, Low-power verification, Emulation, Prototyping

Benefits: Paid vacation, Paid holidays, 401(k) plan with employer match, Employee stock purchase plan, Medical plan, Dental plan, Vision plan