VLSI Timing Methodology Intern - Summer 2027

Job Description

Research and develop compact device and system models to predict time-zero and aged silicon timing behavior in pre-silicon simulations. Apply machine learning and analytical methods to accelerate timing characterization, build tools and methodologies to improve performance and reliability, and investigate physical effects such as IR drop, crosstalk, aging, and thermal impact.

Requirements: Applicants must be pursuing a master's degree or higher in electrical engineering, computer engineering, or a related field, and have knowledge of digital circuit design, MOSFET device physics, and static timing analysis. The role also calls for VLSI backend design experience, understanding of machine learning and statistics, and scripting knowledge in Python, Perl, or Tcl; VLSI internships, compact-model familiarity, and relevant coursework or projects are advantageous.

Key Skills: VLSI Design, Device Modeling, Static Timing Analysis, Digital Circuit Design, MOSFET Device Physics, VLSI Backend Design, Machine Learning, Statistics, Python, Perl, Tcl, BSIM, Timing Characterization, Silicon Performance, Silicon Reliability, CAD Tools

Benefits: Intern Benefits