Need Lead / Senior Verification Engineer / Electrical Engineer / Verification & Validation (V&V) Engineer :: Full-Time

American Cybersystems, Inc. (ACS Group)
US-TX-Austin
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  • Post Date: Aug 06, 2019
  • Job Reference:
  • Start Date: 8/6/2019
  • Job Type: Full-Time

Job Description

Job Details:

Title: Lead / Senior Verification Engineer / Electrical Engineer / Verification & Validation (V&V) Engineer

Location: Hillsboro, OR / Austin, TX / Santa Clara, CA / Chandler, AZ (Multiple Locations)

Duration: Full-Time


Job Description:

  • Master’s/Bachelor’s  Degree in Electrical Engineering with 5+ years of Industry Experience.
  • Experience in creating IP, Full Chip level verification plan and  test-benches from scratch using Verilog/System Verilog/OVM/UVM.
  • Experience in PCIe Gen4 IP verification with Synopsys PHY and VIP.
  • Experience in architecture and validation of CPUs, SOCs and industry standard IPs.
  • Experience with development and usage of BFMs, transactors and protocol checkers used in simulation and HW emulation.
  • Experience with scripting in Perl/TCL/shell to automate flows.
  • Knowledge in IP and SOC development flows and methodologies.
  • Proficient in all aspects of pre-silicon validation (functional, DFT, power, coverage, gate level).
  • Experience in delivering IPs or integrating IPs working with internal and external customers.
  • Create validation plan using product/IP specifications/customer requirements and implementing the necessary verification environment.
  • Expertise in PCIe/Ethernet protocol.

Skills

Job Details:

Title: Lead / Senior Verification Engineer / Electrical Engineer / Verification & Validation (V&V) Engineer

Location: Hillsboro, OR / Austin, TX / Santa Clara, CA / Chandler, AZ (Multiple Locations)

Duration: Full-Time


Job Description:

  • Master’s/Bachelor’s  Degree in Electrical Engineering with 5+ years of Industry Experience.
  • Experience in creating IP, Full Chip level verification plan and  test-benches from scratch using Verilog/System Verilog/OVM/UVM.
  • Experience in PCIe Gen4 IP verification with Synopsys PHY and VIP.
  • Experience in architecture and validation of CPUs, SOCs and industry standard IPs.
  • Experience with development and usage of BFMs, transactors and protocol checkers used in simulation and HW emulation.
  • Experience with scripting in Perl/TCL/shell to automate flows.
  • Knowledge in IP and SOC development flows and methodologies.
  • Proficient in all aspects of pre-silicon validation (functional, DFT, power, coverage, gate level).
  • Experience in delivering IPs or integrating IPs working with internal and external customers.
  • Create validation plan using product/IP specifications/customer requirements and implementing the necessary verification environment.
  • Expertise in PCIe/Ethernet protocol.

Contact Details

Name: Nilesh Awadhiya
Ph: 972-497-2327



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